The invention relates to fractional-N phase locked loops, and more particularly to improving the duty cycle at a frequency divider output in a phase locked loop.
Fractional-N phase locked loops (PLLs) are well known. For example, sigma-delta controlled fractional-N PLL modulators may be used in radio communication systems for generating local oscillator frequencies, with the ability to quickly jump from one operating frequency to another. The fractional-N property permits the use of a high compare frequency while still generating local oscillator frequencies in-between constant multiples of the reference frequency. By controlling the divider ratio with the sigma delta modulator, modulation having a constant envelope can be generated. By using these properties of the fractional-N phase locked loop, radio architectures for constant envelops systems can be developed that are compact enough to enable a complete radio to be integrated on a single applications specific integrated circuit (ASIC).
A block diagram of a prior art sigma-delta controlled fractional-N PLL modulator is depicted in FIG. 1. A reference signal 101 is fed to a phase detector 102 together with the phase of the output of a frequency divider 106. The reference signal 101 is preferably a sinusoidal signal having a frequency denoted by fref. The output of the phase detector 102 is a pulse that is related to the phase difference between the reference signal 101 and the output of the frequency divider 106. The output of the phase detector 102 is fed to a charge pump 107 and then filtered by a loop filter 108. The output of the loop filter 108 is then applied to a voltage controlled oscillator (VCO) 109. The output signal of the VCO 109 is supplied to the input of the frequency divider 106. As a result of this feedback arrangement, the output frequency of the VCO 105 is driven to equal the frequency of the reference signal 101 times the division factor of the frequency divider 106. Hence, the frequency of the VCO 109 can be controlled by controlling the division factor of the frequency divider 106. In a sigma-delta controlled fractional-N PLL modulator, the division factors are generated by a sigma-delta modulator 110, whose input receives a modulating signal 111.
The frequency divider 106 in the PLL has to fulfill three important requirements in order to achieve the desired modulation. First, it must be able to change the division factor once every reference frequency cycle. Second, it must introduce exactly equal delay for all division factors, in order to avoid extra nonlinearities in the loop. Third, it must be able to accomplish a wide range of consecutive division factors in order to make the sigma-delta controlled fractional-N PLL modulator work at a wide range of radio frequencies, and thereby accomplish the multi-band functionality.
To satisfy these requirements, the frequency divider 106 may be implemented in the form of a plurality of series-connected divider blocks, as illustrated in FIG. 2 and described in U.S. Pat. No. 5,948,046, which is hereby incorporated herein by reference in its entirety. Two types of divider blocks are utilized. A first type is any one of the non-presettable ⅔-divider blocks 200a, 200b, 200c, 200d (henceforth referred to generally by the reference number 200). A ⅔-divider block 200 divides the clock input frequency 210a, 210b, 210c, 210d, 210e, 210f, 210g (henceforth referred to generally by the reference number 210) by 2 or 3, depending on the logical values of a first input control signal 211a, 211b, 211c, 211d, 211e (henceforth referred to generally by the reference number 211) and of a corresponding one of a group of second input control signals 207. In some embodiments, the clock inputs 210 may be in the form of differential signals, but this need not be the case in all embodiments. When configured in series with other ⅔-divider blocks 300, first input control signal 211 is generally supplied by a more significant neighboring ⅔ divider block 200. One of these first control signals 211 (e.g., the first control signal 211c) also serves as the output, fFREQ. DIV., from the frequency divider 106.
When used in a continuous phase modulator, such as the one depicted in FIG. 1, the second input control signals 207 are generally derived from the output of the ΣA modulator 110. The second input control signals 207 are used to indicate whether division by two (second control signal=0) or by three (second control signal=1) is requested. However, in order for division by three to be performed, the second control signal 211 must also be set to one. In this sense, the second control signal 211 may be considered a “swallow enable” signal (division by three in the ⅔-divider block 200 is performed by “swallowing” an extra clock cycle in addition to those normally swallowed for division by two).
The multi-divide frequency divider 106 further includes a second type of divider block, herein referred to as a presettable divider block 201a, 201b (henceforth referred to generally by the reference number 201). In the exemplary multi-divide frequency divider of FIG. 2, two presettable divider blocks 201a and 201b, are utilized in the most significant positions of the divider block chain (where the chain comprises both presettable and conventional divider blocks, 201 and 200). The presettable divider block 201 includes the same functionality as the conventional ⅔-divider block 200, and in addition, includes the ability to preset its internal state. Control of the preset option is by means of the On/off signals 208, coordinated with the second control signals 207.
This preset capability is very important for the complete implementation of the multi-divide frequency divider 106, because it provides an opportunity to switch the ⅔-divider block 201, which works like a state machine, on and off into the correct initial state. By doing this, one is able to increase and decrease the possible division factor range of the complete frequency divider 106 at any time during operation. That is, the frequency divider 106 will immediately (within the correct reference cycle) start to divide by the new division factor regardless of whether the wanted division factor is present in the decreased or expanded region. As used here, the term “decreased region” refers to those division factors that are obtainable when none of the presettable divider blocks 201 is enabled. In the exemplary embodiment, the decreased region would be division factors in the range from 16 to 31. As used here, the term “expanded region” refers to those division factors that are obtainable when one or more of the presettable divider blocks 201 is enabled in a divider block chain. In the exemplary embodiment, the expanded region would be division factors in the range from 32 to 63 (when only a first of the presettable divider blocks 201 is active) and from 64 to 95 (when both of the presettable divider blocks 201 is active). It is further noted that in the exemplary embodiment, the divider block 201b, which occupies the most significant position in the string of divider blocks 200, 201, is illustrated as only dividing by “2”. This is accomplished by hard-wiring its second control signal input to always cause a division by “2” to occur. For this reason, it is not illustrated as receiving a second control signal 207.
When using a frequency divider 106 built out of ⅔ divider blocks 200, 201, as shown in FIG. 2, the duty cycle of the frequency divider output signals varies with different input frequencies and divider ratios. For the arrangement depicted in FIG. 2, the frequency divider output duty cycle can be expressed as:             (                        N          /          8                -                  Int          ⁡                      (                          N              /              8                        )                              )        *    8              f      REF        ⁡          (              N        +        16            )      where N denotes the applied integer division factor produced by the modulation block 213. The value “8” that is used in the formula derives from the fact that in the example of FIG. 2, the output signal 211c is supplied by the fourth ⅔ divider block 200d. Had the output signal instead been generated by the third ⅔ divider block 200c, the number “8” would have been replaced by the number “4” in the formula; and, if the output signal instead had instead been generated by the second ⅔ divider block 200b, the number “8” would have been replaced by the number “2” in the formula.
Furthermore, the number “16” in the formula represents the minimum division factor that it is possible to use in a ⅔ divider chain in which 4 blocks are active (i.e., with all blocks set to divide by 2). If only 3 divider blocks were implemented in a ⅔ divider chain, the number “16” would be replaced by the number “8”, and so on.
Ideally, the varying duty cycle should not influence the phase detector 102, but there is always some dependency. For example, consider the dead-band-free phase detector/charge pump combination 300 shown in FIG. 3. The use of first and second digital latches 301, 303 enables multiple states (not shown in FIG. 3) and, hence, an extended range of the phase detector/charge pump combination 300. In operation, the first latch 301 controls whether a first charge pump 305 is on or off. Similarly, the second latch 303 controls whether the second charge pump 307 is on or off. The first and second charge pumps 305, 307 are connected in series, with the phase detector/charge pump output current, iout, being supplied at the connection point between the two charge pumps. The amount of phase detector/charge pump output current, iout, is related to whether none, one, or both of the first and second charge pumps 305, 307 are turned on. The amount of time that iout is non-zero is a function of the phase difference between the two input signals, fref and fFREQ. DIV. Each of these signals is supplied to a clock input of a respective one of the first and second latches 301, 303. The first of these signals to present a clocking edge causes the output of the corresponding latch to be asserted, which in turn, causes a corresponding one of the first and second charge pumps 305, 307 to turn on. When the clocking edge of the remaining input signal is subsequently asserted, it too causes the output of its corresponding latch to be asserted. The outputs of both the first and second latches 301, 303 are further supplied to respective inputs of a logical AND gate 309, whose output is supplied to the input of a delay circuit 311, which delays the signal by an amount ΔT before supplying it to the RESET inputs of both the first and second latches 301, 303. Consequently, when the outputs of both latches 301, 303 are asserted, the output of the AND gate 309 will be asserted as well, thereby resetting both latches 301, 303 after a period of delay, ΔT. They are now initialized to repeat the process again for a next cycle. As a result, the output current iout is either a positive value (being supplied by the first charge pump 305) if the first input signal fref leads the second input signal fFREQ. DIV., or else it is a negative value (being drawn by the second charge pump 307) if the second input signal fFREQ. DIV. leads the first input signal fref.
The reason for the presence of the delay circuit 311 is to eliminate a dead-band that would otherwise characterize the transfer function of the phase detector. The dead-band would result because, when the PLL is properly tracking its reference, fref, both of the phase-detector latches 301, 303 trigger almost simultaneously, due to the fact that the phase difference between the two input signals becomes very small. If there were no delay circuit 311, the reset signal would immediately reset the first and second latches 301, 303 and, as a consequence, only short spikes would appear at the latch outputs, too fast to turn on the respective first and second charge pumps 305, 307. In fact, even if there were a small phase error (i.e., a tracking error), the first and second latches 301, 303 would reset too fast for the charge pumps 305, 307 to react if there were no delay circuit 311 present. Consequently, the phase-detector transfer function would be characterized by a small dead-band (low-gain region) around the origin. With the extra delay provided by the delay circuit 311, the up and down pulses are each long enough to activate the charge pumps 305, 307, thereby eliminating the dead-band.
Returning now to the discussion of how the varying duty cycle of the frequency divider output signal can influence phase detector performance, when the reset pulse of the phase/frequency detector rises, there is a delay until the charge pumps 305, 307 are turned off. This delay, ΔTreset, is illustrated in the timing diagrams depicted in FIG. 4. Depending on whether the frequency divider output signal (denoted fFREQ. DIV.) is high or not when the reset pulse comes, this delay varies. The reason for this is because imperfections that inevitably result when the circuit is implemented in silicon cause the delay through the first and second latches 301, 303 to vary as a function of whether the clock input is high or low. Now, the duty cycle of the frequency divider output signal varies randomly (i.e., it is sometimes high and sometimes low when the reset pulse in the phase detector is generated), which causes random current pulses in the loop filter 108. The current pulses increase the noise level of the complete phase locked loop.
It is therefore desirable to provide techniques and apparatuses that are useful for reducing the influence that the varying duty cycle of the frequency divider output signal has on the performance of the phase detector.